The present invention relates to a semiconductor memory, and more particularly to an Electrically Programmable Read Only Memory (called hereinafter as an "EPROM") in which each of memory cells is formed of an MOS (Metal Oxide Semiconductor) transistor having a control gate electrode and a floating gate electrode.
In an EPROM including such memory cells, a data programming is carried out by supplying a programming (or writing) high voltage in a pulse form to the control electrode and a drain electrode of a selected memory cell to feed a programming current to the drain-source current path of the memory cell from an externally provided programming equipment. Electrons are thereby injected into the floating gate electrode of the selected memory cell, so that the threshold voltage thereof is increased. The programmed memory cell thus obtained is not turned ON by a reading voltage.
Also in the EPROM, a plurality of memory cells are arranged in rows and columns to form a memory cell matrix. The control gate electrodes of the memory cells arranged in the same row are coupled in common to one of word lines and the drain electrodes of the memory cells arranged in the same column are coupled in common to one of digit lines. For this reason, when the programming voltage pulse is supplied to the control gate electrode and the drain electrode of the selected memory cell, a first group of unselected memory cells coupled to the selected word line are also supplied at their control gate electrodes with the programming voltage and a second group of the unselected memory cells coupled to the selected digit line are also supplied at their drain electrodes with that voltage. As a result, in the programmed memory cell or cells among the first group of the unselected memory cells, electrons are carried away from the floating gate electrode to the control gate electrode. In the following, this phenomenon is called as an "FC loss". In the programmed memory cell or cells among the second group of the unselected memory cells, electrons are carried away from the floating gate electrode to the drain electrode. This phenomenon is called hereinafter as an "FD loss". These FC and FD losses are continued during a pulse width of the programming voltage pulse. If the FC or FD loss is large due to the structural defect of the programmed memory cell, the threshold voltage thereof is lowered to a level smaller than the reading voltage, so that the programmed memory cell is changed to an unprogrammed memory cell. Therefore, the FC loss test and the FD loss test are required to detect the lowering in threshold voltages of the programmed memory cells.
In prior art, the FC loss and FD loss tests are carried out in the following manner. First, the EPROM is brought into a programming mode to program all the memory cells. A data reading mode is then carried out in order to ensure whether or not all the memory cells have been programmed. Thereafter, a test voltage that is the same as the programming voltage is supplied to a programming terminal of the EPROM and row address data are changed one by one. The word lines are thereby supplied by ones with the programming voltage. The EPROM is then brought into the data reading mode, and the data stored in all the memory cells are read out. If there exists at least one memory cell having a large FC loss, the data read out from that cell is different from other data. The FC loss test is thus carried out.
The EPROM passing the FC loss test is put to the FD loss test. In this test, the test voltage is supplied again to the programming terminal and column address data are changed one by one. The digit lines are thereby supplied by ones with the programming voltage. The data reading operation is thereafter carried out to read out again the data stored in all the memory cell. If there exists at least one memory cell having a large FD loss, the data read out from that memory cell is different from other data. The EPROM passing the FC loss test and the FD loss test is sold.
Thus, the FC loss and FD loss tests are performed to check data holding characteristics of the memory cells during the programming period.
However, the test according to the prior art requires a considerably long time. More specifically, the programming voltage should be continued to be supplied to the word and digit lines by ones during a time that is equal to the pulse width of the programming voltage pulse. The voltage supplying time to one word line is represented by T.sub.FC and that to one digit line is done by T.sub.FD. Since the numbers of the word and digit lines are N and M, respectively, a time (T.sub.CT) required for supplying the programming voltage to all the word and digit lines are represented as follows: EQU T.sub.CT =N.times.T.sub.FC +M.times.T.sub.FD
Assuming that the EPROM has 512 word lines and 512 digit lines to includes 256K memory cells and the pulse width of the programming voltage pulse is 2 msec (i.e., T.sub.FC =T.sub.FD =2 msec), it takes at least about 2 seconds (=2 msec.times.(512+512)) to carry out the FC and FD tests.